As the traditional scaling of transistors forecast by Moore’s Law has become more difficult and costly, the new frontier for semiconductor development is to find ways to combine different types of chips into one package to make integrated systems that are smaller, faster, more efficient, and more reliable.
But which substrate should these chips (or chiplets, in this context) be mounted upon and interconnected? A substrate large enough for multiple chiplets is needed, and it must also offer high levels of rigidity and flatness, low thermal expansion, and low electrical losses.
In recent years two different substrate technologies – glass core materials and molded redistribution layers (RDLs) — have been the focus of intense research. That research interest was reflected in a special session at the recent 75th annual 2025 IEEE Electronic Components and Technology Conference (ECTC), which drew an overflow, standing-room-only crowd.
“For three quarters of a century, ECTC and its predecessors have served as the world’s leading forum for advancements in microelectronics packaging and component science and technology,” said Przemyslaw Gromala, ECTC 2025 Program Chair and Chief Expert/R&D Project Leader at Robert Bosch GmbH. “This year, our Special Session on glass cores versus RDL interposers drew 350 attendees. It highlighted the urgent need for better substrates to support artificial intelligence (AI), high-performance computing (HPC), advanced systems-on-chips (SoCs), and other fast-growing applications.”
Jan Vardaman, Moderator of the panel and President of TechSearch International, said, “The ECTC panel of experts addressed the main challenges and opportunities in one of today’s most important areas of semiconductor packaging. The panelists gave updates on the state-of-the-art in their specific areas of focus, and offered their views on how these technologies are developing, how fast that is occurring, and the types of applications for which each substrate technology is best suited.”
Glass core substrates have a low coefficient of thermal expansion (CTE), so they offer low warpage and dimensional stability at high temperatures. They also support fine-pitch spacing and high-aspect-ratio vias for high-density interconnects, and provide low electrical losses. But challenges such as singulation without cracking and production of high-layer counts remain. Also, board-level reliability is still under investigation, and economic data on relative cost is lacking.
Molded RDL substrates, meanwhile, are in high-volume production today; are extremely thin which makes them attractive for wearable and other small form factor devices; and offer good electrical performance at lower input/output (I/O) counts. RDL interposers attached to build-up substrates are in production for high-performance applications such as AI inferencing and training and high-end network switches.
The ECTC 2025 Special Session “Glass Core vs. RDL Interposers: Ready for Prime-Time?”
explored how each technology addresses the growing demands for higher performance, larger devices and increased interconnect density. It addressed economic and technical issues for potential high-volume solutions, encompassing design, materials, process/equipment, and metrology.
Zia Karim (Yield Engineering Systems) and Thom Gregorich (Zeiss) co-Chaired the session. The panelists were Richard Bae (Samsung Electro-Mechanics), Gang Duan (Intel), Curt Jackson (Toppan), Akira Tamura (FICT Ltd.), Kathy Yan (TSMC) and Brett Wilkerson (AMD).
Bae from Samsung described the development of build-up layers on a glass core with 40µm laser-fabricated through-glass vias (TGVs). He said that 800µm-thick glass cores have been fabricated; an eight-layer structure for a 640µm thick core with an 80mm x 80mm package body size has been demonstrated; and there is work on 600µm core thickness. He said a pilot line is expected to be completed in Q2 2025, and a 105mm x 105mm package is expected by end of the year with an 840µm core thickness. He noted that board- and system-level reliability are as yet unknown, and that a production line is planned for 2027.
Duan from Intel said that embedded multi-die interconnect bridge (EMIB) and glass core substrates will coexist. He discussed Intel’s demonstration of a glass core substrate with several build-up layers and TGVs in the core having a 1:20 aspect ratio. He called for the industry to develop the glass package ecosystem.
Jackson from Toppan presented a roadmap for meeting the market demands of increased data traffic and low power consumption, going from glass cores in the near future to organic RDLs in the 2030s. He said challenges include back-cracking and second-level reliability for glass cores, as well as the need for a more complete and robust supply chain. He described Toppan’s work in glass core packages, glass interposers, and glass interposers with RDL. For glass core flip-chip ball grid arrays (FCBGAs) targeted at co-packaged optics, he emphasized that a high degree of flatness is important, and that Toppan has been working on ways to decrease the stress on glass with both curing and lithographic approaches.
Tamura from FICT described its process for stacking multiple glass core layers with paste in a single lamination step. The use of the adhesive acts as a stress buffer and helps to minimize CTE differences between the resin and the glass, and the dicing method is modified to reduce stress. Power delivery improvements were noted, and he said the multilayer glass provides more design flexibility than a single glass core.
Yan from TSMC reminded the audience that packages with RDL have been in production for more than 10 years, and described the advantages of organic RDL-based advanced packaging, highlighting its ability to integrate SoC, memory, passive components, and silicon photonic devices. She noted that organic RDL technology offers good electrical performance, high yield, robust reliability, plus the capability to scale-up for HPC or scale-down for edge device applications. Also, that organic RDL technology can be integrated with glass-core substrates for future advanced-packaging applications. She said that TSMC has qualified up to nine layers on CoWoS-R, and demonstrated parts with up to 11 layers. The higher layer counts showed better process yields, and warpage and stress is manageable.
Wilkerson from AMD discussed the advantages of glass panels for carriers, saying that their mechanical stability (flatness, low and tunable CTE, low warpage) opens the possibility of high-volume, low-cost manufacturing based on panel size.
All in all, the panelists noted progress in glass and outlined the remaining challenges, while RDL options in production were discussed. Future debates over packaging options can be expected!
