The 76th annual IEEE Electronic Components and Technology Conference (ECTC) will take place from May 26–29, 2026, at the JW Marriott and Ritz-Carlton Grande Lakes Resort in Orlando, Florida. Recognized as a leading global event for semiconductor packaging, electronic components, and microelectronic systems, ECTC 2026 is expected to gather more than 2,000 scientists and engineers to discuss the latest technical advances and innovative research.
This Tipsheet describes noteworthy talks from the ECTC 2026 technical program:
A) Hybrid Bonding / Heterogeneous Integration
New Density Benchmark for Wafer-to-Wafer Hybrid Bonding: The growing demand for higher bandwidth, lower latency, and improved energy efficiency in high-performance computing and AI accelerators is driving aggressive scaling in 3D packaging technologies. Wafer-to-wafer hybrid bonding has emerged as a critical enabler for next-generation memory architectures, particularly those employing CMOS-bonded-to-array (CBA) designs. Achieving these architectures requires hybrid bonding to deliver sub-0.5µm bond pitch scalability; high yield (>90%) across large via chains with up to 20 million links; and ultra-low leakage across the bond interface.
In this paper, Applied Materials will present the industry’s first successful demonstration of 450nm pitch copper hybrid bonding achieving 98% yield across 20 million via links. This milestone addresses a critical challenge – Because parts-per-million level open defects can significantly degrade wafer-level yield, the researchers used Electron Beam Absorbed Current (EBAC) analysis to identify these open defects. TEM-EELS analysis revealed a thin carbon-rich layer at the Cu-Cu bond interface, coinciding with the presence of large (111)-oriented Cu grains on top and bottom pads. The paper will detail key process optimizations – spanning metallization, chemical mechanical polishing (CMP), plasma treatments, and post-bond annealing – that enabled precise engineering of the grain size and crystal orientation at the bond interface, effectively eliminating the defect. These insights are foundational for further scaling of the hybrid bond pitch below 300nm. (Paper 18.4, “First Demonstration of 450nm Pitch Cu-Cu Hybrid Bonding with 98% Yield Across 20M Interconnects for Ultra-Dense 3D Integration,” Y. Trickett et al, Applied Materials)
Multi-Stacked CMOS Wafer-to-Wafer Direct Bonding for 3D Flash Memory: CMOS directly Bonded to Array (CBA) technology, based on a single CMOS wafer and a cell array wafer, was developed to enhance performance, power, area, and cost (PPAC) in 3D flash memory. A promising technology to provide higher bit density and better I/O performance for 3D flash memory is a wafer-to-wafer Cu direct bonding process for multi-stacked (MS) CMOS and/or cell array CMOS directly Bonded to Array (CBA) structures. The challenge of realizing MS-CBA structures is the necessity of performing the Cu direct bonding process more than twice between wafers exhibiting saddle-shaped warpage. The Cu direct bonding process causes increased misalignment due to this warpage, resulting in bonding failures.
In this paper, KIOXIA will introduce a novel misalignment correction technique in multi-stacked wafer-to-wafer Cu hybrid bonding processes for highly warped wafers, as typically found in 3D NAND and 3D Flash memory applications. These wafers usually have a complex and non-uniform stress distribution that puts extra challenges in the final wafer-to-wafer overlay and significantly impacts the bonding yields. This correction technique for direct bonding of warped wafers will successfully reduce misalignment, and improve the daisy chain yield with sub-800nm pitch bonding pads, electromigration (EM), and stress-induced voiding (SiV). MS-CBA structures using this technique promise to deliver higher memory capacity, higher I/O performance, and higher reliability for 3D flash memories in the near future. (Paper 26.4 “Robust Wafer-to-Wafer Cu Direct Bonding Process for Multi-Stacked CMOS Directly Bonded to Array (CBA) Technology in Future 3D Flash Memory,” M. Tagami et al, KIOXIA)
A Holistic Solution Package to Optimize D2W Bonding Overlay: A high-density metrology equipped with a fixed reference grid enables a precise, die-level grid-based distortion characterization, allowing clear separation of distortion contribution from singulation-induced stress relaxation and the bonding-introduced distortion. By combing reticle-based or stress-based compensation for average die distortion with lithography correction and high-order die shape manipulation to address distortion variability at required stages, substantial overlay improvements are achieved in collective D2W (Co-D2W) hybrid bonding – a key enabler of heterogeneous integration technology.
In this paper, ASML presents a systematic approach to optimize hybrid bonding overlay in die-to-wafer bonding processes through high-precision grid measurements performed at key process steps of the flow. The methodology enables accurate characterization of the die distortion and the identification of major contributors. The impact of critical steps, such as stress relaxation due to die singulation, die placement, and bonding, is quantitively assessed. Based on the die distortion analysis, different correction strategies are proposed and evaluated through simulation, demonstrating less than 80nm bonding overlay performance (simulation results) across heterogeneous dies, marking a key advancement in the precision and scalability of advanced packaging technologies. This bonding overlay is feasible through improved die placement accuracy and symmetric magnification (Ms) correction strategies, such as reticle writing correction, scanner-based precorrection and optimized film stress compensation. (Paper 31.2 “Enabling Scalable Die-to-Wafer Hybrid Bonding Through Die Distortion Correction and Grid Measurement,” A. Hsu et al, ASML)
Indium Electroplated Interconnects for Scalable Heterogeneous Integration: Conventional vapor deposition is widely used, but faces limitations for high-volume manufacturing, including high costs, lengthy vacuum processes, resist patterning challenges at low temperatures, and environmental concerns. Electrochemical deposition has emerged as a cost-efficient and scalable alternative enabling faster deposition at room temperatures, addressing both resist limitations and waste issues. Indium micro-bump interconnects play a key role in heterogeneous integration, particularly in quantum computing and short-wave infrared (SWIR) applications, owing to indium’s low melting point (156.6 °C), high thermal and electrical conductivity, and exceptional ductility at cryogenic temperatures. The drive toward device miniaturization requires ultra-fine pitch interconnections, with current limits approaching a 5µm pitch.
In this paper, CEA-Leti demonstrates the potential of indium-based solder integration for ultra-fine pitch interconnects, using a process flow similar to that of lead-free solder bumps, offering high flexibility in solder material. They describe the complete integration process, including ultra-fine pitch indium plating conditions and seed layer etching. These results highlight the scalability of indium electroplating and its suitability for next-generation interconnects. Key electrochemical parameters on morphology and microstructure, as well as a comparison between electroplated and evaporated indium bumps after integration will also be presented. The research demonstrates a credible, manufacturing‑oriented path to 3µm diameter bumps at 5µm pitch, with detailed optimization across plating, seed etch, coplanarity, intermetallic compound (IMC) behavior, and early flip‑chip results, with clear relevance to chiplets, photonics, and quantum computing. (Paper 21.7, “Electroplated Indium Micro-Bumps: Toward Scalable Low Temperature Ultra-Fine Pitch Interconnects,” M. L. Calvo-Muñoz et al, CEA-Leti)
B) Photonics & Co-Packaged Optics
Active Optical Packaged Substrate Chiplet Integration: Co-packaged optics (CPO) has attracted interest as a solution to overcome the bandwidth and energy-efficiency limitations of electrical interconnects. A key challenge for co-packaged optics (CPO) in microelectronics packages is achieving high-density optical coupling between packaged photonic integrated circuits (PICs) and external optical fibers. Current CPO modules typically rely on direct fiber connections to grating couplers, which limit achievable optical I/O density to a 127µm or more fiber-array pitch, despite the inherently high-density capability of silicon platforms.
In this paper, AIST will describe a successful active transmission demonstration sample using a 50mm2 Active Optical Package (AOP) substrate to overcome optical I/O density constraints by embedding PICs and employing on‑substrate optical redistribution layers (ORDLs). The demonstration sample fully integrates optical components such as 16-channel silicon photonic transceiver chips and micromirrors and polymer ORDL using lithography and imprint technologies. For a 112Gbps (56Gbaud) PAM4 transmission, the measured transmitter and dispersion eye closure quaternary (TDECQ) value was less than 3.4dB, meeting IEEE specifications. The maximum aggregated transmission capacity of the demonstrated AOP substrate is estimated to be 6.4Tbps per substrate. These results demonstrate the feasibility of an optical-first packaging concept and highlight the potential of the AOP substrate as a scalable platform for high-bandwidth integration in future co-packaged optical systems. (Paper 7.4 “Demonstration of an Optical Packaged Substrate with Embedded Silicon Photonic Transceiver for High Performance Chiplet Packaging,” F. Nakamura et al, AIST)
Next Generation Co-Packaged Optics Features Detachable Connector Waveguide: As conventional electrical interconnects struggle to meet increasing requirements for higher bandwidth and energy efficiency driven by AI and high performance computing, optical interconnects have emerged as the next generation solution for high bandwidth interconnects with sustainable power scaling. Co-packaged optics (CPO) – the integration of optical engines at the package level – incorporates silicon photonics to minimize the distance between the optical interface and the integrated circuitry to increase performance and reduce power consumption.
In this paper, GlobalFoundries and Corning will describe a first-of-its-kind passively-integrated detachable connector that leverages the best features of silicon and glass to enable a manufacturable, high power, low loss optical I/O suitable for next-generation co-packaged optics. This approach involves a silicon photonics chip passively integrated with a fully detachable GLASSBRIDGE™ Connector waveguide using ion-exchange technology that leverages on-chip mechanical Z-stops for precise vertical control and lithographic fiducials on both the PIC and glass for accurate X–Y alignment. The resulting interface achieves <1.5dB/facet insertion loss while supporting high power levels (<280mW). This work promises to establish a manufacturable pathway for next-generation co-packaged optics by combining the scalability of GF Fotonix with the modularity and detachability enabled by Corning’s GLASSBRIDGE Connector architecture. The demonstrated performance and assembly repeatability highlight the viability of this approach for high-volume deployment, providing a compelling foundation for future CPO systems requiring low-loss, serviceable, and mechanically integrated optical I/O. (Paper 15.2 “Detachable Glass Waveguide Connector for Co‑Packaged Optics on Silicon Photonics Platform with <1.5dB/Facet Passive Coupling and 280mW Power Handling,” A. Dasgupta et al, GlobalFoundries)
Co-Packaged Optics: Detachable Edge-Coupling Interconnect with Glass Fan-Out Coupler: As the industry transitions from electrical to optical interconnects, driven by AI and data center system scaling, optical coupling solutions that support required bandwidth density, performance, and reliable pluggability are fundamental pillars for co-packaged optics architectures. Recently, electrical systems utilizing 200Gbps serializer/deserializer (SerDes) over copper-based backplanes have been deployed for scale-up solution in rack-scale compute clusters in data centers; however, further scaling of the speed and the number of GPUs in a compute cluster with electrical interconnects will be constrained by challenges in reach, power and density. Hence, the industry is witnessing a transition towards co-packaged optics (CPO) solutions to provide more headroom for scaling.
In this paper, Intel will demonstrate a low loss and high reliability edge-coupling architecture that uses a fan-out glass coupler and the detachable expanded beam connector. This architecture is fully compatible with wafer-level and package-level assembly and test flows, with single direction coupling loss from the fiber to the PIC across all channels of approximately -1.55dB with >100 plug/unplug with extremely minor performance variation far less than 0.01dB with no part failures. Superior loss and reliability test data will be reported to verify the architecture feasibility as well as the modeling and test methodology robustness. (Paper 37.17 “Multi-channel and Multi-scale Optical Performance for a Detachable Edge-Coupling Connector with a Glass Coupler and Expanded Beam in CPO,” Z. Zhang et al, Intel)
C) Assembly and Manufacturing Technology
Scalable Electroplated Copper/Cobalt Metaconductor for Wired GHz Interconnects: The growth of AI has driven demand for ultra-high-speed wired communication in data centers. Current serializer/deserializer links operate at 112Gbps per lane and are transitioning to 224Gbps per lane/multi-lane 400Gbps architectures to sustain bandwidth scaling. This frequency scaling places severe constraints on electrical interconnects embedded within advanced packaging platforms, which must support tens of gigahertz bandwidth while maintaining low insertion loss, high signal integrity, and acceptable energy efficiency. However, as operating frequencies increase, conductor loss becomes the dominant limitation in transmission paths. Even with advanced equalization techniques, forward error correction, and optimized channel design, the increase in AC resistance of copper traces reduces channel reach, degrades eye margin, and increases energy per bit. As a result, conductor-induced attenuation is recognized as a primary bottleneck in scaling electrical links beyond current 112Gbps standards.
In this paper, the University of Florida will present a breakthrough material-based solution that pushes the limits of electrical interconnects toward 400Gbps by dramatically reducing high-frequency conductor loss. Introducing a scalable electroplated copper/cobalt (Cu/Co) multilayer metaconductor interconnect that directly replaces conventional copper wiring without changes to geometry or impedance, the work demonstrates an insertion loss of 0.065dB/mm at 37.5GHz, corresponding to a maximum reduction of 0.087dB/mm, compared to a solid copper interconnect of identical geometry. The ten-pair multilayer structure was fabricated on a low-loss glass substrate using a room-temperature electroplating process compatible with RDLs, interposers, and chiplet-based packages. These results demonstrate a scalable and packaging-compatible material solution for reducing high-frequency conductor loss in next-generation high-speed electrical interconnects. (Paper 11.2 “Scalable Electroplated Cu and Co Metaconductor for Low Loss 112 to 400 Gbps Wired Communication Interconnects,” S. Jeon et al, University of Florida)
Next Generation Panel CMP for Damascene Organic Interposers: Panel-level 2.xD packaging technology combining high bandwidth memory (HBM) with logic on interposers has been adopted for AI and high-end computing applications. As interposers continue to expand to the next-generation 9.5-reticle size, the limitations imposed by the effective area on a circular 300mm wafer is a critical issue. Therefore, the development of organic interposer processes on square glass substrates such as 320 × 320mm and 510 × 515mm panels is anticipated to accommodate finer Cu wiring. While a semi-additive process (SAP) is currently used for re-distribution layer (RDL) Cu wiring, the damascene process is expected to deliver the finer Cu wiring required for HBM4.
In this paper, Resonac will experimentally demonstrate Line/Space (L/S) = 2/2µm organic polymer damascene wiring on 320×320mm glass panels using panel‑level CMP, showing strong practical impact for next‑generation panel‑level organic interposers. By achieving <100nm co‑planarity at Cu/Ti/polymer interfaces via a two‑step CMP (bulk Cu removal followed by barrier-metal CMP) along with optimizing pad groove design and slurry flow distribution for in-plane wiring uniformity, this presents a realistic process solution for HBM4‑class high‑density RDLs. The use of grayscale laser direct imaging (LDI) lithography for simultaneous single-exposure via–trench formation reduces process steps while maintaining dimensional control. Key results include a post‑CMP step height below 100nm at L/S = 2/2μm and successful fabrication of panel‑level test structures, indicating high readiness for volume manufacturing. (Paper 14.2 “Panel CMP Co‑planarization of Heterogeneous Interfaces for Damascene Organic Interposers (L/S = 2/2μm),” K. To et al, Resonac)
First Stitching-Free Fine-Line Lithography for Large Panels: As artificial intelligence applications for semiconductors increase, so does the demand for high-performance, energy-efficient devices. This trend requires heterogeneous integration, which in turn necessitates large-area packaging and fine patterning below 2.0µm line and space (L/S). Conventional lithography techniques for large-area panel level processing require multiple stitching lines on the design or a direct imaging system, which limits productivity/throughput and/or the pattern quality. The larger lithography exposures typically rely on stitching techniques involving forming a large, single package by overlapping the pattern with multiple reticles. A solution is a stitching-free lithography technique on large panels with a fine line lithography process on glass substrates over the entire panel area.
In this paper, USHIO will present a process for stitching-free exposure of an 18-reticle area on 510mm × 515mm glass substrates using a large-area projector lens, enabling precise 1.5µm L/S patterning. Evaluation using the resist employed in back-end processes revealed an ideal process margin of 22µm, accommodating typical variations in the thickness of organic and glass substrates. This 18-reticle area is more four times larger than that of conventional substrate stepper tools and represents a crucial technological foundation for advancing high-performance AI packages. (Paper 28.2 “First Demonstration of Stitching-Free Exposure over an Ultra-Large 18-Reticle Area with High-Resolution 1.5μm Line/Space on Glass Substrates,” N. Sohara et al, USHIO)
Self-Assembling Nanosolder Adhesives for <10µm Interconnects: With the expansion of advanced packaging in AI applications, there is a growing demand for highly-integrated microfabrication of high-performance semiconductor chips. As semiconductor integration reaches its scaling limits, 2.5D/3D heterogeneous integration has emerged as a core strategy in advanced packaging. Currently, high-bandwidth memory (HBM) is in mass production with 20µm pitch and 5µm stack spacing, but the next generation is anticipated to feature I/O pitches as small as 10µm and a stack spacing as narrow as 1µm, requiring interconnects with pitches ranging from 5µm down to 2µm, and potentially even 1µm-class 3D stacked interconnects to meet the ultimate demands of integration density. While hybrid bonding has demonstrated excellent scalability for <10 µm pitch interconnects, its implementation requires tight surface planarity, sub-micron alignment accuracy, and tightly controlled process conditions. Therefore, alternative bonding approaches operating under relaxed process conditions may be required for certain packaging architectures. As demand has grown for innovative bonding material capable of 1µm ultra-fine interconnections with a lower cost structure, research has progressed on nanoparticle synthesis and nanosolder paste, utilizing low melting points and temperature characteristics.
In this paper, Nopion will propose a high-reliability nanosolder-based conductive adhesive (SACA-X) designed to promote thermally assisted particle rearrangement during bonding for >10μm interconnect applications. The engineered nanosolder particles enable self-assembled ultra-fine-pitch interconnections during thermal activation, while a binder resin enhances interlayer bonding reliability. The bonding performance of SACA-X was demonstrated on Si chips with 10µm pads and its feasibility as a next-generation ultra-fine-pitch interconnect material was evaluated. These results demonstrate the feasibility of forming thin (~1µm) metallic interconnections under low-temperature and low-pressure bonding conditions without the need for additional fine-pitch assembly steps. The proposed material system may serve as a complementary interconnection approach for high-density and three-dimensional integration packaging where process simplicity and thermal budget are important considerations. (Paper 29.1 “Game-ChangingNanosolder Technology: Self-Assembling Adhesives for Sub-10µm Ultra-Fine Interconnects,” J.W. Huh et al, Nopion)
D) Reliability
Enhancing CoWoS Reliability Through Fracture Analysis: Epoxy molding compound (EMC) is widely used in microelectronic packaging to protect silicon dies and provide mechanical support, which is critical for the performance and longevity of microelectronic devices. The inherent coefficient of thermal expansion (CTE) mismatch among different materials within semiconductor packaging can induce significant thermal stress, potentially leading to EMC fracture and subsequent interconnect failure. These failure signatures involve cracking and delamination at the EMC/Si die interface, which pose significant risks to package integrity, and highlighting the need for comprehensive analysis of EMC reliability to ensure an understanding of these failure mechanisms.
In this paper, TSMC will describe its use of fracture mechanics–based modeling, in combination with experimental characterization, to investigate the underlying failure mechanisms using their CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technology. The study identifies EMC/Si interfacial delamination occurring at silicon die corners as a dominant concern and demonstrates that interposer stiffness plays a critical role in mitigating failure by reducing CTE mismatch. Experimental methods were also employed to characterize material properties, providing valuable data for enhancing EMC performance. The findings offer actionable insights into mitigating EMC failures and improving packaging reliability, paving the way for optimized designs in next-generation microelectronics. This work contributes to optimized designs for next-generation microelectronics and demonstrates the effective application of fracture mechanics principles in solving important engineering challenges within the field of advanced electronic packaging. (Paper 6.3, “Fracture Analysis for CoWoS Reliability Improvement” M.-C. (Jason) Yew, TSMC)
Advancing Semiconductor Design-for-Reliability Through AI: Current constraints on Design-for-Reliability (DfR) include fragmented experimental parameters, failure criteria, and mechanism interpretations scattered across publications in inconsistent formats. These critical knowledge bottlenecks hinder systematic reuse and cross-study comparison, making evidence difficult to reuse, compare, and audit. Recent advances in artificial intelligence suggest practical routes to address this gap by decomposing complex engineering workflows into specialized, tool-using components using multi-agent large language models (LLMs) to enable decomposition and collaboration across subtasks through role specialization and structured communication enabling agents to interface with external tools and knowledge sources.
In this paper, TU Delft will propose a workflow and framework to utilize dedicated machine learning models operated by agentic AI teams to enable advanced assessment of electronics reliability. They propose a multi-agent framework for transforming this fragmented reliability literature into auditable structured knowledge and actionable experiment recommendations and systematic utilization of implicit domain knowledge through structured knowledge base construction. The comprehensive approach starts with the extraction from existing knowledge from literature and databases, followed by an analysis phase including the addition of new data from experiments purposely advised by an AI agent to recommend expected reliability performance of electronics modules under a given test or mission profile. The paper will describe an example of power electronics IGBT devices to be assessed under power cycling conditions, and details of the workflow will be presented with performance comparisons to known approaches from other projects. (Paper 24.5 “Physics-Constrained Multi-Agent Automation for Design-for-Reliability: From Literature to Auditable Knowledge and Experimental Design” J. Liang, Delft University of Technology)
CoWoS-R Board Level Reliability in Advanced Packaging Accelerator Modules: Among advanced packaging solutions, Chip-on-Wafer-on-Substrate (CoWoS) technology is a widely deployed 2.5D integration platform, enabling large logic dies to be integrated with multi-stack high-bandwidth memory via an interposer. Despite electrical and bandwidth advantages, CoWoS technology introduces challenges to board-level reliability (BLR), due to large reticle size and complex composite materials stack-up, including ball grid array (BGA) fatigue, which can lead to early failure and compromise lifetime reliability. This highlights a critical reliability gap, making it important for silicon foundries to establish BLR awareness and predictive capability for CoWoS technologies to incorporate system-driven reliability into package architecture/assembly design in advanced packaging cycles.
In this paper, TSMC will describe a comprehensive exploration of board level performance and failure mechanisms in CoWoS-R advanced packaging, temperature cycling testing (TCT), vibration, and shock testing conducted on 3.3X-reticle CoWoS-R packages on Open Compute Project (OCP) Accelerator Module (OAM) boards. The impact of temperature difference and dwell time on package lifetime during TCT is characterized, and TCT is identified as a critical modulator of BLR, inducing severe BGA cracks on both substrate and PCB sides. A finite element analysis (FEA) model was developed to simulate thermal cycling stress and identify BGA fatigue hot zone on a 3.3X CoWoS-R package and compared fatigue risks from FEA models using bulk, regional, and trace-mapping PCB material properties to study the impact of material mapping resolution on BLR TC simulation results. (Paper 37.15 “A Holistic Study of Board Level Reliability of CoWoS-R Advanced Packaging on OCP Accelerator Modules,” T-Y. Wu et al, TSMC)
Reliability for 2.5D Chiplet Integration in Automotive Applications: As 2.5D packaging is playing an increasing role in automotive semiconductors, one of the challenges is ensuring reliability, especially with the adoption of micro-Cu pillar bumps for chiplet integration. Although micro-bump technology is prevalent in conventional flip chip ball grid array (FCBGA) microelectronic applications with demonstrated reliability, comprehensive studies are limited regarding reliability of micro-bumps in automotive applications. To support next-generation automotive systems with enhanced connectivity, chiplet-based System-on-Chip (SoC) architectures are emerging as a key enabling technology; however, achieving automotive-grade reliability remains a major barrier to their deployment in automotive chiplet SoCs. Integrating multiple chiplets enables scalable product configurations and flexible performance scaling to significantly reduce development costs and shorten time-to-market.
In this paper, Renesas will describe a prototype 2.5D package utilizing an organic interposer to evaluate reliability of micro-bumps connecting the die to the interposer. The micro-bump structure consists of a Cu/Ni/Cu/solder configuration, with diameters of 25, 28, 45, 50, and 58μm. The results demonstrate that intermetallic alloying effectively mitigates electromigration (EM) degradation. However, as the diameter of the micro-bumps decreases (due to tin depletion), increased resistivity associated with alloying becomes more significant at the elevated temperatures common in automotive environments. This research underscores the importance of precise control over both alloy composition and micro-bump geometry to increase reliability using organic interposers, and provides practical guidelines for the optimization of micro-bumps in future automotive chiplet SoCs. (Paper 35.3, “Automotive Reliability of Micro-Cu Pillar Bumps for 2.5D Chiplet Integration,” K. Ando et al, Renesas)
