Alphawave Semi Partners to Showcase AI Connectivity at Supercomputing 2024

 Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, will showcase its latest advances in AI and connectivity technology at the 2024 Supercomputing Conference (SC24) for advances in data centers, AI/ML, HPC, networking storage and analysis technologies.

The Supercomputing Conference takes place at Atlanta’s Georgia World Congress Center, from November 17 to 22. For the event, Alphawave Semi has partnered with PCI-SIG, the CXL Consortium, the UCIe Consortium, and the interconnect providers Lessengers and Samtec, with key demonstrations taking place across the show floor.

Demonstrations of advanced AI connectivity advances

• Industry’s first showing of Alphawave Semi’s upcoming I/O chiplet with UCIe, Ethernet, PCIe and CXL for SoCs targeting high-bandwidth applications including AI, HPC and hyperscale data centers.

Demo location: Open Standards Pavilion, UCIe Consortium, booth 1815

• PCIe Gen7 over copper, with 128 Gbps PAM4 SerDes transmissions. This will demonstrate Gen7 capabilities in near chip, high density connectors, similar to a GPU-GPU connection for an accelerator. Driven at over 40 dB loss and showing a healthy BER margin, it highlights plenty of headroom for future designs.

Demo location: Samtec, booth 1125

• 106 Gbps PAM4 SerDes transmission over immersion-cooled pluggable optical interconnects, driving a high-density interconnect to simulate future GPU-to-GPU connectivity. This highly configurable SerDes IP is ready for customer tape out, supports all leading edge NRZ and PAM4 data center standards and is silicon proven in 7, 6, 5, 4 and 3nm processes.

Demo location: Lessengers, booth 609

• 64 GT/s PCIe 6.0 interoperability and robustness testing between Alphawave Semi’s PipeCore PCIe 6.0 subsystem and Keysight. This demonstration features Alphawave Semi’s leading-edge silicon implementation of the new PCIe 6.0 64 GT/s Flow Control Unit (FLIT)-based protocol and enables higher data rates for hyperscale and data infrastructure applications.

Demo location: PCI-SIG, booth 3354

• PCIe 6.0 subsystem supporting OSFP-XD PCIe direct attach cabling, with a >40 dB high-density interconnect driven at 64 Gbps to enable new CopprLink architectures. The IP addresses the next generation of low latency compute interfaces for AI and machine learning and collaborations with Amphenol demonstrate this in action over a more-than 4.0 m OSFP-XD Amphenol direct attach copper and shows a healthy BER margin when compared to specification (1E-6).

Demo location: CXL Consortium, booth 1807

• Energy-efficient accelerator cards to demonstrate the potential of chiplet-to-chiplet optical connectivity with Alphawave Semi’s Arm Neoverse Compute Chiplet, the AlphaCHIP1600 I/O Chiplet, and IP Subsystems. This incorporates UCIe, HBM, Ethernet, PCIe, CXL, and SerDes to create an accelerated path for specialized CPU solutions for Arm-powered AI and machine learning infrastructure.