The IEEE/JSAP Symposium on VLSI Technology & Circuits has delivered a unique convergence of technology and circuits in the microelectronics industry for the last 45 years, creating maximum synergy between both domains. The 2026 Symposium is dedicated to the theme: “Advancing the AI Frontier Through VLSI Innovation.” The five-day event will be held in-person, featuring live sessions at the Hilton Hawaiian Village, Honolulu, HI, from June 14 to 18, 2026, and OnDemand access to technical sessions and other content beginning the following week. The Symposium will feature the latest VLSI technology developments, innovative circuit design, and the applications they enable, such as artificial intelligence, machine learning, IoT, wearable/implantable biomedical applications, big data, cloud/edge computing, virtual reality (VR) / augmented reality (AR), robotics, and autonomous vehicles.
The Symposium continues to be the microelectronics industry’s premiere international conference integrating technology, circuits, and systems with a range and scope like no other conference. In addition to the technical presentations, the Symposium program will feature a demonstration session, an evening panel discussion, joint focus sessions, short courses, and workshops that provide technical content relevant to the Symposium theme.
Plenary Sessions
“Building the Engine of AI: From Foundational VLSI Technologies to System-Scale Impact,” by Dr. Richard Ho, Head of Hardware, OpenAI
New AI models are rapidly advancing intelligence across entertainment, productivity, and scientific discovery, driving transformative impact worldwide. However, the growing demands of large-scale training and inference are placing significant stress on hardware systems. To scale AI for global benefit, critical challenges in compute, memory bandwidth, connectivity, and datacenter infrastructure must be addressed. Achieving this will require innovations in memory integration, low-power interconnects, power delivery, thermal management, and advanced packaging – co-optimized within unified system architectures. Only through holistic, system-level design and disciplined execution can the necessary improvements in performance, efficiency, and total cost of ownership be realized to make AI broadly accessible.
“Advanced Package for Next-Generation AI System Scaling” by Dr. L.C. Lu, Senior Fellow & VP of R&D, TSMC
Advanced packaging is becoming central to scaling next-generation AI systems, addressing increasing demands for performance, power efficiency, and bandwidth. As compute density rises, communication bandwidth is the top priority, driven by continued UCIe advancements in 2.5D packaging. Silicon photonics innovations further improve energy-efficient, high-speed interconnects across AI datacenters. With multi-layer 3D stacking emerging as a mainstream integration approach, thermal management and power delivery become critical constraints. Solutions such as optimized cooling strategies and vertical power delivery networks help mitigate these challenges by reducing heat and improving efficiency. Meanwhile, 3Dblox plays a key role in enabling interoperable 3DIC design and automated heterogeneous integration through ongoing IEEE standardization efforts.
“Intelligence Accelerated: Memory Innovations to Power the AI Era,” by Dr. Nirmal Ramaswamy, Corporate Vice President, Micron Technology
Artificial intelligence is fueling rapid growth in compute, data movement, and energy use, with memory now emerging as the primary bottleneck in advanced systems. As trillion-parameter models and reasoning workloads demand higher bandwidth and lower latency, the industry must advance DRAM, NAND, and high-bandwidth memory alongside innovations in packaging, including hybrid bonding and 3D stacking. Progress will depend on breakthroughs in materials science, modeling, wafer bonding, and metrology. Emerging non-volatile memories and CXL-based architectures will enable more flexible, scalable systems. Together, these innovations will define the next decade of AI infrastructure, delivering the performance and efficiency required for continued growth.
“Meeting AI Demand Through Equipment Innovation and AI-Driven Manufacturing: Progress and Challenges” by Mr. Yoshinobu Mitano, Corporate Officer, Executive VP & General Manager, Tokyo Electron Ltd.|
The semiconductor industry has grown alongside advancements in manufacturing equipment, and the rise of AI is further expanding the role of semiconductors. Equipment not only enables AI system performance but is also increasingly enhanced by AI itself, improving fab operations and technology. This presentation highlights efforts on both fronts: how new equipment and process innovations drive higher-performance, lower-power AI systems, and how AI is applied to optimize equipment and manufacturing. Current progress, challenges, and next steps are outlined, demonstrating how a dual approach – advancing both semiconductors and equipment with AI – can meet today’s and tomorrow’s AI demands.
Focus Sessions
The Symposium program integrates technology & circuit topics with a series of six joint focus sessions to present papers that encompass both areas, including: 1) New computing and quantum computing; 2) Design-Technology Co-Optimization (DTCO); 3) Advanced STCO and AI/ML; 4) High Performance Computing (HPC) Connectivity; 5) Power Management; 6) Sensors, Imagers, & Displays. In addition, there are two Technology focus sessions on: 1) Advanced 3D Logic; 2) 3D Memory (Flash & HBM) Technology.
Short Courses on Critical VLSI topics
Two full-day short courses will be featured:
• Technology Short Course – “Technologies Shaping the Future as Key Enablers for AI” will cover Advanced Logic Technology Scaling, 3D Augmented Dimensional Scaling, Heterogeneous Integration, Material / Process Integration Innovations for AI, Beyond 6F2 – Scaling Frontiers and Future DRAM, Emerging NV Memories, Oxide Semiconductors for 3D Integration, and Advanced Optical Interconnects for AI Computing.
• Circuits Short Course – “AI-Driven Design Acceleration: Learning Across Circuits, Technology, and Yield” will examine Analog EDA, AI for Memory Development, Agent AI in EDA, Practical AI-Driven Floor Planning, AI Assistant for AI Analog IC Design, Machine Learning in Diagnosis, The Future of Chip Design, and General Transformation Re-engineering VLSI.
Joint Evening Panel Session
“AI: Grand Vision or Grand Delusion?”
Moderators:
• Gary Bronner, Senior VP, Rambus Labs
• Vita Pi-Ho Hu, Professor of Electrical Engineering, National Taiwan University
Panelists:
• Tom Burd, Senior Fellow, AMD
• Kazunari Ishimaru, CTO & Senior Managing Executive Officer, Rapidus
• David Kanter, President & Founder, Real World Insights / ML Commons
• Hoshik Kim, Senior VP, Memory Systems Research, SK hynix
• Raja Koduri, Founder & CEO, Oxmiq Labs
The AI industry faces a pivotal moment as ambitious scaling goals collide with physical and economic limits. OpenAI’s call for trillion-dollar AI infrastructure investments underscores the massive expansion needed in datacenters, fabrication, and energy generation. While inference drives monetization, the costs and power demands – potentially hundreds of gigawatts by the 2030s – raise questions about the feasibility and efficiency of current strategies. The sector must weigh whether scaling compute for Large Language Models will fulfill AI’s promise or risk a “dot.AI” bubble. Realizing AI’s transformative potential may require paradigm shifts in computational approaches, not just raw expansion.
Demonstration Session
Approximately 15–20 table-top presentations will demonstrate device characterization, chip operational results, and potential applications for circuit-level innovations. Introduced in 2017, this popular in-person demonstration session will provide participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. The best demo will be selected by Symposium attendees.
Workshops
A series of workshop sessions will be held during the Symposium program to provide additional learning opportunities on topics adjacent to the Symposium program. This year, there are six workshops:
Workshop Sessions 1
• Advances in Cryo-CMOS: Devices, Circuits and Applications
• Embedded Memories in the Sub-2nm Era: SRAM Scaling Perspectives, Alternatives, & 3D Futures
• Combining Light and Logic: Electronic–Photonic Co-Design for High-Performance Systems
Workshop Sessions 2
• Design, System and Cross-Technology Co Optimization for Silicon Spin Qubits
• High-Performance CMOS for DRAM: Enabling Mobile, Graphics, Datacenter, & HBM in the AI Era
• VLSI Device Manufacturability: Improving Semiconductor Yield Through Virtualization
Luncheon Presentation
“Innovative Neurotechnologies – A Journey from the Lab to the Clinic and Back” by Dr. Madjid HiHi, CEA-Leti
The CEA-Leti Clinatec biomedical center in Grenoble exemplifies the power of translational ecosystems that unite neuroscientists, engineers, and clinicians to advance neurotechnology. Clinatec has developed the WIMAGINE wireless electrocorticography system for long-term clinical use, benefiting motor-disabled patients. World-first demonstrations have paired WIMAGINE® with exoskeletons and spinal cord stimulators to restore mobility, leading to industrial transfer to ONWARD Medical in 2024. Future applications include stroke neurorehabilitation using motor rehabilitation systems. Converging advances in microelectronics, high-density electrodes, and embedded AI are driving autonomous neuroprostheses, enabling real-time decoding of motor intentions and redefining seamless, lifelong brain-machine integration.
Special events at the Symposium include mentoring events sponsored by the Solid-State Circuits Society for Women in Circuits and for Young Professionals. In addition, a Young Professionals event sponsored jointly by the Hawaii Sections (June 14 of the Solid-State Circuits Society and the Electron Devices Society will be held.
Satellite Workshops held in conjunction with the Symposium include the 2026 Silicon Nanoelectronics Workshop (June 13 & 14), sponsored by the IEEE Electron Devices Society; and the 2026 Spintronic Workshop on LSI (June 14), organized by the Center for Innovative Integrated Electronic Systems (CIES), the Research Institute of Electrical Communication (RIEC), and the Center for Science and Innovation in Spintronics (CSIS) as World-Leading Research Center for Spintronics at Tohoku University.
Best Student Paper Awards for each track Symposium are chosen based on the quality of the papers and presentations. The recipients will receive a monetary award, travel cost support, and a certificate. For a paper to be reviewed for this award, the lead author and presenter of the paper must be enrolled as a full-time student at the time of submission and must indicate on the web submission form that the paper is a student paper.
