Solving Capacitive Load Instability in Push-Pull Voltage Supervisors—Part 1: Identifying the Problem

Abstract

Push-pull voltage supervisors offer key advantages, including fast reset response, rail-to-rail logic levels, and simplified designs without external pull up resistors. However, when higher-voltage rails are monitored using a resistor divider, capacitive loads at the output can introduce periodic transients that prevent the system from reaching a stable state.

This first article of the series identifies common sources of capacitive loading, explains the mechanism behind the resulting instability, and demonstrates its effects in two representative applications.

Introduction

Voltage supervisors monitor supply rails, prevent system faults, and protect downstream circuits. Analog Devices offers a broad portfolio of supervisors with configurable thresholds, multiple output topologies, and tailored timing options to address a wide range of application requirements.

A key difference among supervisors is how the trip point is set. Factory-trimmed supervisors have a fixed threshold defined during production, allowing direct connection to the monitored rail without external resistors. This simplifies design and improves accuracy, especially in reliability-critical applications.

Resistor-programmable supervisors use external resistors to set the trip point. This adds flexibility but introduces extra components and sensitivity to resistor tolerance.

This configuration requires care. Capacitive loads—originating from connected device inputs (C1) or PCB parasitics (C2)—can interact with the push-pull output and resistor divider, causing instability. The following sections explain why this occurs, beginning with push-pull output operation.

In some applications—particularly when reusing a proven part or when board constraints favor a given topology—a factory-trimmed supervisor may be used with a resistor divider to monitor a higher-voltage rail. For example, the MAX809T, a 3-lead active-low microprocessor reset circuit trimmed to a 3.08V undervoltage threshold, can monitor a 12V rail by scaling it to 3.24V at the V_CC pin, as shown in Figure 1.

Operation of Push-Pull Voltage Supervisors

Push-pull supervisors are well-suited for compact designs that require fast response. Their output is driven by complementary MOSFETs that switch based on the voltage at V_CC.

In an active-low configuration, when V_CC rises above the under-voltage threshold during startup, the reset output is driven high. The p-channel MOSFET turns on, sourcing current from V_CC. This push phase is shown in red in Figure 2.

When V_CC falls below the threshold, the reset output is driven low. The n-channel MOSFET turns on and sinks current to ground. This is the pull phase, shown in blue in Figure 2.

This operation assumes an ideal high-impedance load. In practice, the load often includes a significant capacitive component. When the output transitions high, the capacitor must be charged from a discharged state. At that instant, an uncharged capacitor presents near-zero impedance—effectively a short circuit—causing a large initial surge of current to flow from the V_CC pin into the load. This inrush current is the root cause of the instability discussed next.

Sources of Capacitive Loads in Supervisory Circuits

Capacitive loads at the supervisor output can arise from several sources, both inherent and design-driven. Understanding each is important for anticipating stability risks.

Input Pin Capacitance

FPGA, microcontroller, and complex programmable logic device (CPLD) input pins exhibit inherent capacitance specified in data sheets. Typical values range from a few picofarads to tens of picofarads and may reach hundreds of picofarads, depending on the I/O standard and pin type. This unavoidable capacitance is represented by C1 in Figure 1 and must be factored into system design.

PCB Parasitic Capacitance

Signal traces routed across a PCB introduce parasitic capacitance, particularly when running parallel to ground planes over long distances. Longer traces increase capacitance, represented by C2 in Figure 1. Unlike pin capacitance, this can be reduced with careful layout and routing.

Intentional Capacitive Elements

Some designs intentionally add capacitance at RESET to create timing delays or drive sequencing logic. RC networks used to delay other IC enable inputs (for example, EN, CE, or SHDN pins) or control downstream power are common examples. Although intentional, this capacitance can still trigger instability and must be treated carefully.

The Instability Mechanism: A Feedback Loop Between Output and Supply

To understand why capacitive loading causes instability, it is necessary to trace the current path during the push phase—specifically, where the inrush current for charging the output capacitor comes from.

During reset deassertion, the p-channel MOSFET sources current from the V_CC pin to charge the output capacitance. The inrush current is highest at the moment of switching, when the capacitor is fully discharged.

When V_CC is tied to the monitored rail itself, the current is drawn from a relatively stiff supply that can tolerate the transient without significant voltage deviation. However, when a resistor divider is used to scale a higher voltage down to V_CC, the V_CC node becomes a high-impedance node. The inrush current is drawn through this divider, causing a transient voltage dip at the V_CC pin.

This is the crux of the problem: if the V_CC dip is large enough and long enough to cross below the undervoltage threshold, the device interprets it as a genuine supply fault and immediately reasserts. The capacitor discharges, V_CC recovers, and the supervisor attempts to deassert again. The cycle then repeats indefinitely.

This creates a self-sustaining feedback loop: the attempt to deassert causes a supply glitch that triggers another reset, preventing the system from ever settling. The monitored rail itself can remain perfectly stable throughout the process.

The depth of the V_CC dip depends on the load capacitance, the divider impedance, and the current drive capability of the push-pull output. In some configurations, capacitance as low as 70pF is sufficient to trigger oscillation.

Instability in Practice: Two Application Scenarios

Scenario 1: Board Parasitic and Load Pin Capacitance (MAX809T)

Consider the MAX809T configured with a resistor divider to monitor a 12V rail. Using R1 = 4.7kΩ and R2 = 1.74kΩ, the V_CC pin is set to 3.24V under normal operating conditions:

Since the MAX809T’s undervoltage threshold is 3.08V, the monitored rail will trip at:

Under normal operation, RESET deasserts once the supply exceeds this level. However, when a CPLD or FPGA I/O with ~70pF of input capacitance is connected to RESET, the start-up behavior changes entirely.

As shown in Figure 3, the 12V rail reaches steady state, and the V_CC pin settles to 3.24V as expected. Yet the reset output never successfully deasserts. Additional board-level parasitic capacitance from PCB traces compounds the effect, increasing the total capacitance seen by the output and making the instability more severe.

Scenario 2: Intentional RC Load (MAX6421)

A second and equally important scenario arises when the reset output is used not merely as a logic signal, but as a driver for downstream circuitry. Figure 4 shows the MAX6421 driving a MOSFET gate through an RC network to generate a delayed, inverted enable signal.

The MAX6421 monitors a 10V rail with a trip point set to 9.07V, which corresponds to 2.9V at the V_CC pin. During startup, when the monitored voltage exceeds 2.9V, the reset output begins to deassert. In theory, should charge C4 through R4 with a time constant τ = R4 × C4, reaching approximately 63% of its final value after one time constant and fully charging after 5τ.

In practice, this ideal behavior is never observed. As RESET sources current to charge C4, the resulting inrush current through the divider causes a transient dip at the V_CC pin. This dip crosses below the 2.9V undervoltage threshold, causing the supervisor to reassert RESET. The capacitor partially discharges, V_CC recovers, and the output attempts to deassert again. The cycle repeats persistently, as captured in Figure 5.

Notably, the monitored supply rail remains completely stable at 10V throughout this instability—confirming that the oscillation is entirely a consequence of the capacitive load and the feedback mechanism at V_CC, not any external supply disturbance.

Figure 6 zooms into a single deassertion attempt to reveal what is happening at each spike. The sequence is clear: the output begins to rise, inrush current flows from V_CC into the output capacitor, V_CC dips transiently below the 2.9V under-voltage threshold, and the supervisor immediately reasserts before deassertion completes. This single cycle then repeats indefinitely.

Design Takeaways—Part 1

• A push-pull RESET output is a low-impedance source during deassertion
• A resistor-divider-derived V_CC creates an internal feedback path
• Capacitive loading can trigger false undervoltage detection
• The supply rail may be fully stable while RESET oscillates continuously
• Even modest capacitance, originating from device inputs, PCB parasitics, or intentional RC networks, can cause instability when divider impedance is high

Conclusion

Push-pull voltage supervisors offer compelling advantages for voltage monitoring applications, but the interaction between capacitive loads and the resistor divider introduces a feedback mechanism that can prevent stable operation entirely. The root cause is not a fault in the supply being monitored, but a transient current draw at the V_CC node during the push phase—a phenomenon that repeats cyclically once triggered.

Since eliminating all capacitance from the reset output is rarely practical in real-world designs, this instability must be anticipated and addressed at the design stage. The second article in this series will examine the physics of this feedback mechanism in greater depth and present practical mitigation strategies—including the role of series resistance and supply bypass capacitance—that restore stable operation across a range of capacitive load conditions.

About the Authors

Lord Gaell Gelacio is a product applications engineer in the Industrial, Power, and Precision Group at Analog Devices, where he supports high-performance supervisory products. He joined Analog Devices in May 2024. Prior to ADI, he worked as a hardware engineer and research associate at the University of the Philippines Diliman, where he contributed to the development of the first metrology-grade air quality monitor designed and developed in the Philippines. He holds a Bachelor of Science degree in electrical engineering, with a major in electronics engineering, from the University of the Philippines.

Noel Tenorio is a senior product applications manager in the Industrial, Power, and Precision Group at Analog Devices Philippines, leading the applications team that supports high-performance supervisory circuits, protection circuits, and other cross-business-unit power product portfolios. He joined ADI in August 2016. Prior to ADI, he worked for six years as a design engineer in a switch-mode power supply research and development organization. He earned a Bachelor of Science degree in electronics and communications engineering from Batangas State University, a postgraduate degree in electrical engineering with a major in power electronics, and a Master of Science degree in electronics engineering from Mapúa University. He has authored and co-authored technical publications on improving power-system reliability using voltage supervisory circuits and holds one U.S. patent related to thermoelectric cooler controller products.